1. Field of the Invention
The present invention relates to a semiconductor packaged device and a lead frame for use within the semiconductor packaged device. More particularly, the present invention relates to a semiconductor packaged device using a lead frame in which the leads of the lead frame extend in two directions from a semiconductor chip.
2. Description of the Related Art
Recently, there has developed a high demand for semiconductor packaged memory devices having increased density and functions. In addition, the demand is also great for developing devices which have a plurality of memory regions (i.e., value added or multi-bit devices). However, as the density and function of the device is increased and as more memories are added, the size of the memory chip is likely to increase as well. One way to avoid such an increase in the size of a packaged memory device is to use, for example, an LOC (lead on chip) structure.
FIGS. 1A and 1B illustrate a prior art semiconductor packaged memory device adopting an LOC structure. FIG. 1A is a plan view showing the inside of the semiconductor packaged device, while FIG. 1B is a cross-sectional view taken along the line IB--IB of FIG. 1A.
As illustrated in FIG. 1A, leads 3 of a lead frame are adhered to the surface of a semiconductor chip 1 by a tape 2. The chip 1 may comprise, for example, a center pad structure. Each of the leads 3 has an inner lead portion 3a which is connected to a respective electrode pad 1a by a corresponding bonding wire 4. The semiconductor chip 1 and its outer periphery is then sealed in mold resin 5.
The resin, however, is less able to fill the area above the chip 1 where the leads 3 are formed than it is able to fill the area under the chip 1. Thus it has been necessary to increase the amount of resin in the area above the chip 1. The problem with this approach is that the device becomes easily warped. The warping of the device will occur because the thickness of the resin above the chip, as compared to the resin thickness below it, will be different.
This problem particularly concerns a multi-bit memory having a plurality of memory regions since it has a larger number of leads, as compared to a single-bit memory. For instance, as shown in FIGS. 1A and 1B, the semiconductor packaged device having a multi-bit memory may be constructed such that the leads 3 have outer lead portions 3b extending in two opposing directions from the semiconductor chip 1. The mold resin 5 will then be considerably thicker in each of these directions where the chip 1 is not present. Furthermore, the warp will vary in shape between the area in the mold resin 5 where the chip 1 is present and that area where the chip 1 is not present. This variation in the warp occurs because the thickness of the mold resin 5 will be different for these two areas.
More specifically, in the area where the chip 1 is present, the resin under the chip 1 will be thinner than that above it. Thus, the resin above the chip will contract more when the resin hardens, causing the packaged device to warp concavely. In the area where the chip 1 is not present, on the other hand, the leads 3 will be formed above the center line CL (drawn half-way between the upper surface and undersurface of the packaged device). Thus, the resin under the leads 3 will contract more when the resin hardens, causing the device to warp convexly. Therefore, these different warps will cause cracking in the semiconductor packaged device which is unfavorable for its manufacture.
As described above, the prior art semiconductor packaged device has the drawback that warping easily occurs when an LOC structure is used to reduce the size of the packaged device. Therefore, it is an object of the present invention to provide a semiconductor packaged device, having an LOC structure and using a lead frame, which is capable of decreasing a warp.